1. Field of the Invention
This invention relates to bipolar memory cells employing merged transistor logic (MTL) in the form of modified integrated Schottky logic (ISL).
2. Prior Art
S. K. Wiedmann et al in "Session XVII: Random Access Memories", ISSCC (IEEE Feb. 15, 1980) and "Session XII: Memory Techniques" ISSCC (IEEE Feb. 19, 1981) have disclosed the structure and use of high density static memories with extremely low power dissipation using integrated injection logic/merged transistor logic (I.sup.2 L/MTL).
FIGS. 1 and 2 depict the basic Wiedmann et al cell 10 (including bit lines 12 and 14, and word line 16) in schematic and cross section, respectively. As FIG. 1 shows, Wiedmann et al succeeded in eliminating resistors from cell 10 and feeding cell 10 with power through bit lines 12 and 14 (power flow is shown by current sources 18 and 20). The absence of resistors in the basic cell affords high packing density since resistors require physically distinct regions from the active device regions of cell transistors T.sub.1 and T.sub.2.
Further, in order to keep the power dissipated by static cell 10 low, the standby current must be very low. For a given supply voltage, this implies a need for a very high resistance (i.e. at least megahoms or possibly 10.sup.12 ohms) to minimize the standby current, which in turn requires large chip areas due to limitations on the sheet resistance of materials.
Feeding power and current to the cells through the bit lines allows two resistors (i.e., the resistances associated with current sources 18 and 20) to serve the same function for an entire column of memory cells as the resistors (not shown) normally included in each memory cell. This allows reduction of the overall size of the semiconductor memory for a given supply voltage as compared to memories where each cell includes its own power supply, while keeping the power dissipated the same.
Wiedmann et al provide power to T.sub.1 and T.sub.2 by using current injecting transistors T.sub.3 and T.sub.4. Transistors T.sub.1 and T.sub.3 form a first half of cell 10 (marked by dashed line 22). Likewise transistors T.sub.2 and T.sub.4 form the second half of cell 10, both halves being identical.
Each pair of transistors (i.e., T.sub.1 and T.sub.3, and T.sub.2 and T.sub.4) are connected in I.sup.2 L/MTL configuration. This configuration is well known. T.sub.1 and T.sub.2 are connected with their collector and base regions in the familiar cross-coupled relationship to provide a bistable, regenerative circuit. However for I.sup.2 L, T.sub.1 and T.sub.2 operate in the inverse mode (i.e., current flow is in the direction which affords low current gain as contrasted with the normal or forward mode where current flows in the direction which affords high current gain). Processing of I.sup.2 L transistor configurations is more limited than the processing of configurations where the resulting transistors operate in the forward current mode because of the restrictions on doping profiles for I.sup.2 L.
The cross section in FIG. 2 includes only the first half of cell 10 marked by line 22. The base, emitter and collector regions of T.sub.1 and T.sub.3 are similarly numbered in FIGS. 1 and 2. Current I.sub.i represents the inverse current flow in T.sub.1. As is well known, the current gain .beta. (i.e, collector current divided by base current) of a semiconductor transistor operating in the inverse mode is on the order of 2 to 10. However, .beta. for a transistor operating with normal or forward current flow is on the order of 20 to 100, or ten times that of I.sup.2 L. Thus base current in normally operating semiconductor transistors can be an order of magnitude less than base currents in inverse operating semiconductor transistors in order to provide the same collector current. Also a .beta. in the range of 50 is generally desired to insure stable, reproducible current conditions in a memory cell. Packing density is limited in I.sup.2 L due to limitations on the base width (see w in FIG. 2) of the lateral transistor.
To achieve high packing density, low standby current and low power dissipation, it is therefore highly desirable to provide a bipolar memory cell having no resistors in the basic cell structure, which is fed with power through the bit lines and which employs transistors operating in the normal or forward current mode.
Also known is integrated Schottky logic (ISL). J. Lohstroh in "ISL, a Fast and Dense Low-Power Logic, made in a Standard Schottky Process", IEEE Journal of Solid State Circuits, Vol. SC-14 No. 3, June 1979, discloses the schematic and cross sections of FIGS. 3 and 4, respectively. Similar structure is like numbered between FIGS. 3 and 4 for clarity.
In FIG. 3 a merged n-p-n transistor T.sub.5 and p-n-p transistor T.sub.6 are shown. T.sub.5 is adapted to be switched between a saturated mode and an off condition by an input signal at 34. To avoid heavy saturation of T.sub.5 (thus avoiding a large delay in switching to the off condition) Lohstrom employs clamping transistor T.sub.6. T.sub.6 drains off most of the T.sub.5 input current as soon as the T.sub.6 base-collector junction becomes forward biased. T.sub.5 still goes into saturation but not as heavily. Transistor T.sub.5 operates in the normal current mode. Schottky diodes 36, 38, 40 and 42 complete the basic ISL structure.
Lohstroh refines the device of FIG. 3 by forming T.sub.6 as a composite of two p-n-p transistors T.sub.7 and T.sub.8 as shown in FIG. 4. By making the base of T.sub.7 thinner than the base of T.sub.8, the logic gate speed can be improved. Note that Lohstroh's basic design requires a gap d between buried N+ tub 44 and isolation barrier 46 in order for vertical p-n-p transistor T.sub.8 to be formed.
Since ISL operates in the normal current mode, it affords easier processing and wider applicability than I.sup.2 L. ISL as proposed by Lohstroh, or as refined, has not heretofore been employed in bipolar memory cells.